FIG. 9 is a simplified cross-sectional view showing an exemplary conventional floating-gate transistor (cell) 50 formed on a silicon substrate 51 using, e.g., conventional CMOS fabrication techniques. Floating-gate cell 50 includes an N+ doped source region S and an N+ doped drain region D that are formed in substrate 51 and are separated by a P-type channel region C. Formed over substrate 51 is a gate oxide layer 53, a polycrystalline silicone (polysilicon) floating gate FG disposed on gate oxide layer 53, an a control gate CG that is separated from floating gate FG by a second oxide layer 55. Oxide layers 53 and 55 completely surround floating gate FG, so that floating gate FG is electrically isolated. Program and erase (unprogram) operations are usually performed using Fowler-Nordheim Tunneling or Hot-Carrier Injection mechanisms that are known in the art, and are not relevant to the present invention. The resulting charge applied to floating gate FG during a program or erase operation is trapped on floating gate FG for long periods of time, even when power is turned off, thus making floating gate cells “non-volatile”.
FIG. 9 indicates voltages and signals generated during a read operation in which the programmed/unprogrammed state of floating-gate cell 50 is selectively determined, whereby the “data” stored on floating-gate cell 50 is “read”. The read operation involves applying a bias voltage VBIAS to control gate CG, and measuring voltage drop between drain region D and source region S, e.g., by coupling source region S to a ground potential, and measuring output signal VOUT at drain region D. Ideally, bias voltage VBIAS is higher than the threshold voltage of floating-gate cell 50 when it is unprogrammed, but lower than the threshold of floating-gate cell 50 when it is programmed. That is, when floating gate FG is programmed, the combined electric field generated by control gate CG (under the influence of bias voltage VBIAS) and floating gate FG is insufficient to pass current from drain region D to source region S, whereby output signal VOUT remains high. Conversely, when floating gate FG is unprogrammed, the combined electric field generated by control gate CG (under the influence of bias voltage VBIAS) and floating gate FG is sufficient to pass current from source region S to drain region D, whereby output signal VOUT is low.
Floating-gate cells are best known for storing large amounts of data in dedicated non-volatile memory devices such as Erasible Programmable Read-Only Memory (EPROM) devices, Electrically Erasible Programmable Read-Only Memory (EEPROM) devices and “flash” memory devices. However, smaller numbers of floating-gate cells are often incorporated into many types of otherwise “volatile” IC circuits to store trim, configuration and other data associated with a desired operation of the IC device. Such smaller numbers of floating-gate cells are often referred to as being “embedded”, and are collectively referred to herein as “embedded EPROM”.
Embedded EPROMs typically require special process steps that are not part of standard CMOS process flows, and as such the embedded EPROMs must be tested to assure that they function properly (i.e., as described above). However, as the number of functions designed into an IC device increases, the number of input-output pins (I/O pins) of the IC device also increases correspondingly, and it is often not desirable or feasible to increase the pin count of an IC device to perform special functions, such as testing a relatively small number of floating-gate cells associated with an embedded EPROM. The pin count of an IC device is often limited by the size and design of IC packages in which the IC chip is assembled. A large pin count increases the size and the cost for packaging the IC. Therefore, there is often a limit on the amount of I/O pins an IC has to perform all of the functions required to both test and operate the IC.
What is needed is a test system and method for evaluating embedded EPROMs that avoids the need for additional I/O pins and minimizes test time.